发明名称 静止電流(IDDQ)指示および試験装置および方法
摘要 <p>An embodiment of an electronic device includes a logic circuit, a switching element, and a quiescent current (IDDQ) evaluation circuit. The logic circuit is coupled to a first ground node. The switching element is coupled between the first ground node and a second ground node. The switching element is configurable in an electrically non-conductive state when the electronic device is in an IDDQ evaluation state, and in an electrically conductive state when the electronic device is not in the IDDQ evaluation state. When the electronic device is in the IDDQ evaluation state, the IDDQ evaluation circuit is configured to provide a first output signal when an IDDQ indicating voltage across the first and second ground nodes exceeds a reference voltage. Other embodiments include methods for producing an indication of IDDQ in an electronic device and methods for fabricating an electronic device with the capability of producing an IDDQ indication.</p>
申请公布号 JP5785194(B2) 申请公布日期 2015.09.24
申请号 JP20120551199 申请日期 2011.01.19
申请人 发明人
分类号 G01R31/28;G01R31/26 主分类号 G01R31/28
代理机构 代理人
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