Scalable serializer

摘要

According to an exemplary embodiment, a serializer includes upper and lower shift registers configured to perform a load function where parallel input data is loaded from a parallel input bus and a shift function where the parallel input data is shifted to an output register. The upper shift register is configured to perform the load function while the lower shift register performs the shift function, and the lower shift register is configured to perform the load function while the upper shift register performs the shift function. An output register is configured to alternately receive the parallel input data from the upper shift register and the parallel input data from the lower shift register. The upper and lower shift registers and the output register can comprise scan flip-flops.

主权项

1. A serializer comprising:
upper and lower shift registers configured to perform a load function wherein parallel input data is loaded from a parallel input bus and a shift function wherein said parallel input data is shifted to an output register; said output register configured to alternately receive all of said parallel input data from said upper shift register followed by all of said parallel input data from said lower shift register over a plurality of consecutive time periods.