发明名称 High-performance cache system and method
摘要 A digital system includes a processor core and a cache control unit. The processor core can be coupled to a first memory containing data and a second memory with a faster speed than the first memory, and is configured to execute a segment of instructions having at least one instruction accessing the data from the second memory using a base register. The cache control unit is configured to be coupled to the first memory, the second memory, and the processor core to fill the data from the first memory to the second memory before the processor core executes the instruction accessing the data, and is further configured to examine the segment of instructions to extract instruction information containing at least data access instruction information and last register updating instruction information and to create a track corresponding to the segment of instructions based on the extracted instruction information.
申请公布号 US9141388(B2) 申请公布日期 2015.09.22
申请号 US201213549394 申请日期 2012.07.13
申请人 SHANGHAI XIN HAO MICRO ELECTRONICS CO., LTD. 发明人 Lin Kenneth Chenghao;Ren Haoqi
分类号 G06F12/08;G06F9/38;G06F9/30;G06F9/32 主分类号 G06F12/08
代理机构 Anova Law Group, PLLC 代理人 Anova Law Group, PLLC
主权项 1. A digital system, comprising: a processor core capable of being coupled to a first memory containing data and a second memory with a faster speed than the first memory, and configured to execute a segment of instructions having at least one instruction accessing the data from the second memory using a base register; and a cache control unit configured to be coupled to the first memory, the second memory, and the processor core to fill the data from the first memory to the second memory before the processor core executes the instruction accessing the data, wherein the cache control unit is further configured to: examine the segment of instructions to extract instruction information containing at least data access instruction information and last register updating instruction information;create a track corresponding to the segment of instructions based on the extracted instruction information; andfill the data from the first memory to the second memory based on the track corresponding to the segment of instructions after execution of an instruction last updating the base register used by the at least one instruction accessing the data.
地址 Shanghai CN