发明名称 |
FPGA packet processing engine |
摘要 |
A graphic processor device is implemented on a field programmable gate array (“FPGA”) circuitry comprises a pipeline formatter that sets graphic commands and vertex data into structures, and a rasterizer that interpolates between vertices in the vertex data to generate lines and filling between at least one edge to generate a structure, wherein output of the rasterizer is a stream of fragments that become pixels. The graphic processor device further includes a frame buffer that receives a stream of fragments and blends a plurality of fragments before the plurality of fragments are stored in a frame buffer, and an output processor configured to retrieve a plurality of fragments from the frame buffer and transmits a plurality of pixels according to a predefined resolution. |
申请公布号 |
US9142002(B2) |
申请公布日期 |
2015.09.22 |
申请号 |
US201213363738 |
申请日期 |
2012.02.01 |
申请人 |
L-3 COMMUNICATIONS CORPORATION |
发明人 |
Dutton Marcus Franklin |
分类号 |
G06T15/00;G06T1/20 |
主分类号 |
G06T15/00 |
代理机构 |
Gardner Groff Greenwald & Villanueva, P.C. |
代理人 |
Gardner Groff Greenwald & Villanueva, P.C. |
主权项 |
1. A graphic processor device implemented on a field programmable gate array circuitry, comprising:
a pipeline formatter that sets graphic commands and vertex data into structures; a rasterizer that interpolates between vertices in the vertex data to generate lines and filling between at least one edge to generate a structure, wherein an output of the rasterizer is a stream of fragments that become pixels; a frame buffer operator that receives the stream of fragments and blends a plurality of fragments before the plurality of fragments are stored in a frame buffer memory that is external to the graphic processor device, wherein the frame buffer operator also blends at least one of the plurality of fragments with a fragment that is already stored in the external frame buffer memory; a frame buffer manager that is in bidirectional communication with and controls the external frame buffer memory, wherein the external frame buffer memory includes a front buffer which is used for receiving graphics from the graphic processor device and a back buffer which is used for transmitting graphics from the graphic processor device; and an output processor configured to retrieve the plurality of fragments from the frame buffer manager and transmit a plurality of pixels according to a predefined resolution. |
地址 |
New York NY US |