Calibration of inter-slice gain and offset errors in time-interleaved analog-to- digital converter

摘要

An analog input signal is dithered using a dithering sequence and then partially chopped using a chopping sequence. The dithered and partially chopped signal is then digitized by analog-to-digital converter (ADC) slices operating in alternating fashion, and the resulting digitized signals are adjusted according to the dithering sequence and the chopping sequence to compensate for gain and voltage offset errors of the ADC slices.

主权项

1. A method of operating an interleaved analog-to-digital converter (ADC) comprising a plurality of ADC slices, comprising:
adding a dither to an analog input signal based on a dither sequence, and thereafter splitting the analog input signal into first and second signal components; transmitting the respective first and second signal components through a first signal path and a second signal path; chopping the second signal component in the second signal path using a chopping sequence to produce a chopped second signal component; recombining the chopped second signal component with the first signal component to produce a composite signal; digitizing the composite signal by operating the ADC slices in an alternating fashion to produce a plurality of digital samples; adjusting the digital samples according to estimated voltage offset errors of the ADC slices determined in relation to the dither sequence and the chopping sequence; and adjusting the digital samples according to estimated gain errors of the ADC slices determined in relation to the dither sequence and the chopping sequence.