Memory circuitry using write assist voltage boost

摘要

Within a memory 2 comprising an array 4 of bit cells 6 write driver circuitry 14 uses a boosted write signal which is boosted to a lower than normal level during a write operation. Column select transistors 16 are driven by column select circuitry 12. The column select signal is boosted to a lower than normal level when a column is unselected and to higher than a normal level when a column is selected. Voltage boost circuitry, such as charge pumps 20, 22 are employed within the column select circuitry 12 to achieve these boosted levels for the columns select signal.

主权项

1. Memory circuitry comprising:
an array of bit cells; a plurality of bit lines, each of said plurality of bit lines coupled to a column of bit cells within said array; write driver circuitry selectively coupled to each of said bit lines through a respective column select transistor controlled by a column select signal, said write driver circuitry supplying write signal with a write voltage level outside of a voltage range between a first voltage level and a second voltage level in order to perform a write operation within said array; column select circuitry coupled to a power supply via a first power supply rail at said first voltage level and a second power supply rail at said second voltage level, said first voltage level being higher than said second voltage level, said column select circuitry being configured to select one or more target columns of bit cells within to which a write operation is to be performed by:
(i) supplying a column select signal with a selected signal level to respective column select transistors for said one or more target columns, said selected signal level holding said respective column select transistor for said one or more target columns in a low impedance state; and(ii) supplying a column select signal with an unselected signal level to respective column select transistors for one or more unselected columns within said array other than said one or more target columns, said unselected signal level holding said respective column select transistor for said one or more other columns in a high impedance state; wherein at least one of said selected signal level and said unselected signal level is outside of said voltage range between said first voltage level and said second voltage level.