JESD test sequencer generator

摘要

A framer interfacing between one or more data converters and a logic device is disclosed. The framer comprises a transport layer and a data link layer, and the framer is configured to frame one or more samples from the data converters to frames according to a serialized interface. In particular, the synthesis of the hardware for the framer is parameterizable, and within the synthesized hardware, one or more software configurations are possible. Instance parameters used in synthesizing the framer may include at least one of: the size of the input bus for providing one or more samples to the transport layer, the total number of bits per converter, and the number of lanes for the link. Furthermore, a transport layer test sequence generator for inserting a test sequence in the transport layer is disclosed.

主权项

1. An apparatus for generating test sequences to allow verification of a framer, wherein the framer is configured to interface between one or more data converters and a logic device and to provide a plurality of frames to the logic device according to a serialized interface, the apparatus comprising:
a transport layer test sequence generator on hardware configured to:
generate a transport layer test sequence according to a specification of the framer, wherein the specification includes a number of bits per converter, a number of data converter(s), and a number of sample(s) per converter per frame, and the transport layer test sequence comprises one or more converter identifiers, one or more sample identifiers, and a shifted pattern of control bits over the plurality of frames; andreplace one or more samples from the one or more data converters with the transport layer test sequence; wherein the transport layer test sequence generator is synthesized to hardware based on the specification of the framer.