发明名称 Reconfigurable wideband sub-ranging analog-to-digital converter
摘要 A reconfigurable wideband analog-to-digital converter (ADC) system comprising a first converter stage having a first signal path including a first sample and hold circuit for sampling an input signal at a first resolution, and a second signal path responsive to the input signal and arranged in parallel with the first signal path. The second signal path includes a second sample and hold circuit for sampling the input signal at a second resolution. A first ADC is also included for generating a digital representation of the input signal sampled by the first converter stage. A control processor is arranged between outputs of the first and second sample and hold circuits and the input of the ADC for selectively providing the signal sampled by one of the first or second sample and hold circuit to the input of the ADC.
申请公布号 US9143146(B1) 申请公布日期 2015.09.22
申请号 US201414479946 申请日期 2014.09.08
申请人 Lockheed Martin Corporation 发明人 Pereira Victoria Tabuena;Linder Lloyd Frederick;Robl Douglas A.;Davis Brandon R.;Omori Toshi
分类号 H03M1/12;H03M1/08;H03M1/68 主分类号 H03M1/12
代理机构 Howard IP Law Group, PC 代理人 Howard IP Law Group, PC
主权项 1. A reconfigurable wideband analog-to-digital converter (ADC) system comprising: a first converter stage including: a first signal path including a first sample and hold circuit for sampling an input signal at a first resolution;a second signal path arranged in parallel with the first signal path, the second signal path including a second sample and hold circuit for sampling the input signal at a second resolution; a second converter stage including at least one sample and hold circuit arranged in series with an output of at least one of the first or second sample and hold circuits; a first ADC arranged in parallel with the second converter stage and configured to generate a digital representation of the sampled input signal from the first or second sample and hold circuit; and a control circuit arranged in parallel with the second converter stage and between outputs of the first and second sample and hold circuits and an input of the first ADC and configured to selectively provide the sampled input signals generated by the first or second sample and hold circuit to the input of the first ADC.
地址 Bethesda MD US