发明名称 |
Data processing system with latency tolerance execution |
摘要 |
In a processor having an instruction unit, a decode/issue unit, and execution queues configured to provide instructions to correspondingly different types execution units, a method comprises maintaining a duplicate free list for the execution queues. The duplicate free list includes a plurality of duplicate dependent instruction indicators that indicate when a duplicate instruction for a dependent instruction is stored in at least one of the execution queues. One of the duplicate dependent instruction indicators is assigned to an execution queue for a dependent instruction. The dependent instruction is executed only when the one of the duplicate dependent instruction indicators is reset. |
申请公布号 |
US9141391(B2) |
申请公布日期 |
2015.09.22 |
申请号 |
US201213419531 |
申请日期 |
2012.03.14 |
申请人 |
Freescale Semiconductor, Inc. |
发明人 |
Tran Thang M.;Nguyen Trinh Huy |
分类号 |
G06F15/00;G06F9/30;G06F9/40;G06F9/38 |
主分类号 |
G06F15/00 |
代理机构 |
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代理人 |
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主权项 |
1. In a processor having an instruction unit, a decode/issue unit, and execution queues configured to provide instructions to correspondingly different types execution units, a method comprising:
maintaining a duplicate free list for the execution queues, wherein the duplicate free list includes a plurality of duplicate dependent instruction indicators that indicate when a duplicate instruction for a dependent instruction is stored in at least one of the execution queues; assigning one of the duplicate dependent instruction indicators to an execution queue for a dependent instruction; and executing the dependent instruction only when the one of the duplicate dependent instruction indicators is reset. |
地址 |
Austin TX US |