Multi-function delay locked loop

摘要

A delay circuit provides a quadrature-delayed strobe, a tightly controlled quadrature DLL and write/read leveling delay lines by using the same physical delay line pair. By multiplexing different usage models, the need for multiple delay lines is significantly reduced to only two delay lines per byte. As a result, the delay circuit provides substantial saving in terms of layout area and power.

主权项

1. A delay circuit comprising:
a delay line configured to receive a clock signal and output a delayed clock signal; a delay controller configured to control the delay line to output the delayed clock signal at a quadrature delay relative to the clock signal; a multiplexer receiving a plurality of delay signals, the delay signals including the clock signal and the delayed clock signals; a state machine configured to control the multiplexer to select one of the delay signals to provide signal leveling among a plurality of associated output signals; and a second delay line configured to receive a data strobe signal and output a delayed data strobe signal.