Phase locked loop frequency synthesizer with reduced jitter

摘要

A phase locked loop frequency synthesizer has a controlled oscillator for generating an output signal at a desired frequency, a phase/frequency detector module for comparing a feedback signal derived from the controlled oscillator with a reference signal to generate an error signal, a loop filter for processing said at least one error signal from said phase/frequency detector module to generate a combined control signal for the controlled oscillator. The gain of the phase/frequency detector module can be adjusted, preferably by varying the pulse width and pulse cycle, to maintain the overall gain of the phase locked loop within a given range and thereby maximize signal to noise ratio.

主权项

1. A phase locked loop frequency synthesizer comprising:
a controlled oscillator for generating an output signal at an operating frequency; a phase/frequency detector module with variable gain configured to compare a feedback signal derived from the controlled oscillator with a reference signal to generate an error signal having a pulse width representative of a delay between said feedback signal and said reference signal, whereby the pulse width for a given error signal is determined by the gain of said phase/frequency detector module; said phase/frequency detector module comprising a chain of serially coupled phase/frequency detector sub-modules, each sub-module outputting a signal having a pulse width that for a given error signal incrementally increases at respective outputs of the sub-modules along the chain; a loop filter for processing said at least one error signal from said phase/frequency detector module to generate a control signal for the controlled oscillator; and a selection module for adjusting the gain of said phase/frequency detector module in accordance with a programmable threshold based on the operating frequency by switching between outputs of said sub-modules to provide said error signal.