Chip package and fabrication method thereof

摘要

An embodiment of the present invention relates to a chip package and fabrication method thereof, which includes a semiconductor substrate containing a chip area and a peripheral pad area surrounding the chip area, wherein a conductive pad and a through hole exposing the conductive pad are formed in the peripheral pad area; a protection layer covering a bottom surface of the semiconductor substrate and the through hole; a packaging layer formed on an upper surface of the semiconductor substrate; and a spacing layer formed between the packaging layer and the semiconductor substrate, wherein the chip packaging has a main side surface constituted of side surfaces of the semiconductor substrate, the protecting layer, the packaging layer and the spacing layer, and wherein the main side surface has at least one recess portion.

主权项

1. A chip package, comprising:
a semiconductor substrate containing a chip area and a peripheral pad area surrounding the chip area, wherein a conductive pad and a through hole exposing the conductive pad are formed in the peripheral pad area; a protection layer covering a bottom surface of the semiconductor substrate and the through hole; a packaging layer formed on an upper surface of the semiconductor substrate, wherein the packaging layer is a substrate; and a spacing layer formed between the packaging layer and the semiconductor substrate, wherein the spacing layer is a non-electrically conductive material, wherein the chip packaging has a main side surface constituted of side surfaces of the semiconductor substrate, the protection layer, the packaging layer and the spacing layer, and wherein the main side surface has at least one recess portion at the packaging layer, wherein the packaging layer has a foot portion under the recess portion, and wherein a sidewall of the foot portion is aligned with a sidewall of the semiconductor substrate.