Method and Circuit for Improving the Settling Time of an Output Stage

摘要

The present document relates to amplifiers, notably multi-stage amplifiers, such as linear regulators or linear voltage regulators (e.g. low-dropout regulators) configured to provide a constant output voltage subject to load transients. An amplifier comprising an output stage for providing an output current at an output voltage, in dependence of an input voltage at a stage input node of the output stage, is described. The output stage comprises a first input transistor; wherein a gate of the first input transistor is coupled to the stage input node of the output stage. Furthermore, the output stage comprises a first diode transistor; wherein the first diode transistor is arranged in series with the input transistor. In addition, the output stage comprises a pass device configured to provide the output current at the output voltage; wherein the first diode transistor and the pass device form a current mirror.

主权项

1) An amplifier comprising an output stage for providing an output current at an output voltage, in dependence of an input voltage at a stage input node of the output stage; wherein the output stage comprises
a first input transistor; wherein a gate of the first input transistor is coupled to the stage input node of the output stage; a first diode transistor; wherein the first diode transistor is arranged in series with the input transistor; a pass device configured to provide the output current at the output voltage; wherein the first diode transistor and the pass device form a current mirror; wherein a midpoint between the first input transistor and the first diode transistor is coupled to a gate node of the pass device; a second input transistor; wherein a gate of the second input transistor is coupled to the stage input node of the output stage; wherein the second input transistor is configured to control a voltage level at a replica node, in dependence of the input voltage; and a buffer transistor; wherein a gate of the buffer transistor is coupled to the replica node and wherein an input node of the buffer transistor is coupled to the gate node, such that the buffer transistor is configured to sink or source a charge current at the gate node, subject to the voltage level at the replica node and the voltage level at the gate node.