CLOCK PULSE GENERATOR FOR MULTI-PHASE SIGNALING

摘要

A clock generator is provided that is immune to skew between bits in digital words generated by a multi-phase receiver.

主权项

1. A circuit, comprising:
a pull-down signal generator configured to generate a plurality of pull-down signals corresponding to a plurality of digital words; a plurality of pull-down circuits corresponding to the plurality of pull-down signals, each pull-down circuit configured to discharge a common node for a first delay responsive to an assertion of the corresponding pull-down signal by the pull-down signal generator; a pull-up circuit configured to bias the common node to a power supply voltage after a second delay from the discharge of the common node.