发明名称 SEMICONDUCTOR DEVICE AND DRIVING METHOD THEREOF
摘要 A semiconductor device in which operation delay can be suppressed is provided. The semiconductor device includes a first logic element, a second logic element, a first circuit that has a function of controlling conduction between the first logic element and the second logic element, and a fourth circuit. The fourth circuit is electrically connected to the first circuit, and is electrically connected to the second logic element.
申请公布号 US2015263734(A1) 申请公布日期 2015.09.17
申请号 US201514643288 申请日期 2015.03.10
申请人 Semiconductor Energy Laboratory Co., Ltd. 发明人 OKAMOTO Yuki;KUROKAWA Yoshiyuki
分类号 H03K19/0185;H03K19/0944 主分类号 H03K19/0185
代理机构 代理人
主权项 1. A driving method of a semiconductor device, the semiconductor device comprising: a first logic element;a second logic element;a first circuit comprising a second circuit and a third circuit; anda first wiring,wherein each of the second circuit and the third circuit comprises: a first transistor;a second transistor;a third transistor; anda capacitor,wherein one of a source and a drain of the first transistor is electrically connected to the first wiring,wherein the other of the source and the drain of the first transistor is electrically connected to one electrode of the capacitor and a gate of the second transistor,wherein one of a source and a drain of the second transistor is electrically connected to the first logic element,wherein the other of the source and the drain of the second transistor is electrically connected to one of a source and a drain of the third transistor, andwherein the other of the source and the drain of the third transistor is electrically connected to the second logic element, the driving method comprising: a first period in which the third transistor in the third circuit remains off, wherein the first period includes a second period and a third period after the second period, wherein in the second period, the first transistor in the third circuit is turned on, a low potential is input to the one of the source and the drain of the second transistor in the third circuit and a high potential is input to the gate of the second transistor in the third circuit via the first transistor and the first wiring, wherein in the third period, second configuration data is written into the third circuit via the first wiring, and wherein conduction or non-conduction between the first logic element and the second logic element is set in accordance with first configuration data stored in the second circuit during the second period and the third period.
地址 Atsugi-shi JP