SOLID-STATE IMAGE CAPTURING APPARATUS, METHOD OF MANUFACTURING THE SAME, AND CAMERA

摘要

A solid-state image capturing apparatus, comprising a semiconductor substrate including a first region of a first conductivity type, charge accumulation regions of a second conductivity type, transistors each outputting a signal based on charges accumulated in the charge accumulation region, a second region of the first conductivity type formed in a position deeper than the charge accumulation regions and shallower than the first region so as to be electrically conducted to the first region, whose impurity concentration is higher than that of the first region, and a third region of the second conductivity type formed between the second region and the first region, wherein the second region is formed across a region including two or more transistors in a planar view and supplies a current to each of the two or more transistors.

主权项

1. A solid-state image capturing apparatus comprising:
a substrate including a first semiconductor region of a first conductivity type; a plurality of charge accumulation regions of a second conductivity type formed in the semiconductor substrate; a plurality of transistors formed in a semiconductor substrate, each configured to output a signal based on a charge accumulated in corresponding one of the plurality of charge accumulation regions; a second semiconductor region of the first conductivity type formed in a position deeper than the charge accumulation regions of the semiconductor substrate and shallower than the first semiconductor region, electrically conducted to the first semiconductor region, and having an impurity concentration higher than that of the first semiconductor region; and a third semiconductor region of the second conductivity type formed between the second semiconductor region and the first semiconductor region, and receiving a first power supply voltage, wherein the second semiconductor region is formed across a region including two or more transistors of the plurality of transistors in a planar view with respect to an upper surface of the semiconductor substrate, and is configured to supply a current to the two or more transistors upon receiving a second power supply voltage different from the first power supply voltage.