| 发明名称 |
SEMICONDUCTOR MEMORY DEVICE |
| 摘要 |
A memory device includes first and second memory cell arrays, and a control circuit configured to output first information indicating whether the first memory cell array is in a ready state in which the control circuit is ready to receive a command to access the first memory cell array or a busy state in which the control circuit is not ready to receive the command to access the first memory cell array, and second information indicating whether the second memory cell array is in a ready state in which the control circuit is ready to receive a command to access the second memory cell array or a busy state in which the control circuit is not ready to receive the command to access the second memory cell array. |
| 申请公布号 |
US2015262630(A1) |
申请公布日期 |
2015.09.17 |
| 申请号 |
US201414475493 |
申请日期 |
2014.09.02 |
| 申请人 |
KABUSHIKI KAISHA TOSHIBA |
发明人 |
SHIRAKAWA Masanobu;HARA Tokumasa |
| 分类号 |
G11C7/10;G11C7/24;G06F12/08 |
主分类号 |
G11C7/10 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A semiconductor memory device comprising:
first and second memory cell arrays; and a control circuit configured to output first information indicating whether the first memory cell array is in a ready state in which the control circuit is ready to receive a command to access the first memory cell array or a busy state in which the control circuit is not ready to receive the command to access the first memory cell array, and second information indicating whether the second memory cell array is in a ready state in which the control circuit is ready to receive a command to access the second memory cell array or a busy state in which the control circuit is not ready to receive the command to access the second memory cell array. |
| 地址 |
Tokyo JP |
