RESISTANCE CHANGE MEMORY

摘要

According to one embodiment, first normal bit and source lines are connected to a first memory cell. Second normal bit and source lines are connected to a second memory cell. A first column switch connects one of the first and second normal bit lines to a first global bit line. A second column switch connects one of the first and second normal source lines to a first global source line. A first reference bit and source lines are connected to a third memory cell. A third column switch connects the first reference bit line to a second global bit line. A fourth column switch connects the first reference source line to the first global source line. A sense amplifier is connected to the first and second global bit lines, and reads data stored in one of the first and second memory cells.

主权项

1. A resistance change memory comprising:
a first memory cell array arranged with memory cells having resistance change elements; a first normal bit line connected to one end of a first memory cell in the first memory cell array; a first normal source line connected to the other end of the first memory cell; a second normal bit line connected to one end of a second memory cell in the first memory cell array; a second normal source line connected to the other end of the second memory cell; a first column switch configured to select one of the first and second normal bit lines, and connect the selected one of the first and second normal bit lines to a first global bit line; a second column switch configured to select one of the first and second normal source lines, and connect the selected one of the first and second normal source lines to a first global source line; a first reference bit line connected to one end of a third memory cell in the first memory cell array; a first reference source line connected to the other end of the third memory cell; a third column switch configured to connect the first reference bit line to a second global bit line; a fourth column switch configured to connect the first reference source line to the first global source line; and a first sense amplifier connected to the first global bit line and the second global bit line, and configured to read data stored in any one of the first and second memory cells.