发明名称 |
VARIABLE RESISTANCE MEMORY AND THE METHOD OF CONTROLLING THE SAME |
摘要 |
According to one embodiment, a variable resistance memory including a bit line extending in a first direction, a word line extending in a second direction, and a memory cell array including memory cells, each of the memory cells including a variable resistance element and a selective transistor, the element being configured to store two-bit data using a change in resistance, the element being connected to the bit line, a gate of the selective transistor being connected to the word line, wherein a first and a second write current are selectively applied to the element, to enable the data to be written, and a first and a second read current are selectively applied to the element, to enable the data to be read. |
申请公布号 |
US2015263068(A1) |
申请公布日期 |
2015.09.17 |
申请号 |
US201414479018 |
申请日期 |
2014.09.05 |
申请人 |
KABUSHIKI KAISHA TOSHIBA |
发明人 |
ITO Yuichi |
分类号 |
H01L27/22;H01L43/08;G11C11/16;H01L43/02 |
主分类号 |
H01L27/22 |
代理机构 |
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代理人 |
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主权项 |
1. A variable resistance memory comprising:
a bit line extending in a first direction; a first word line extending in a second direction intersecting with the first direction; and a memory cell array including memory cells arranged in a matrix, each of the memory cells including a variable resistance element and at least one selective transistor, the variable resistance element being configured to store two-bit data using a change in resistance, the variable resistance element having an end connected to the bit line, and another end connected to a drain of the selective transistor, a source of the selective transistor being connected to a source line, a gate of the selective transistor being connected to the first word line, wherein a first write current and a second write current being greater than the first write current are selectively applied to the variable resistance element using the selective transistor, to enable the data to be written; and a first read current and a second read current being greater than the first read current are selectively applied to the variable resistance element using the selective transistor, to enable the data to be read. |
地址 |
Tokyo JP |