MULTI SUPPLY CELL ARRAYS FOR LOW POWER DESIGNS

摘要

A MOS device includes a number of standard cells configured to reduce routing congestions while providing area savings on the MOS device. The standard cells may be single height standard cells that share an n-type well isolated from other nearby n-type wells. The input and output signal pins of the single height standard cells may be configured in a lowest possible metal layer (e.g., M1), while the secondary power pins of the single height standard cells may be configured in a higher metal layer (e.g., M2). Interconnects supplying power to secondary power pins may be configured along vertical tracks and shared among different sets of standard cells, which may reduce the number of vertical tracks used in the MOS device. The number of available horizontal routing tracks in the MOS device may remain unaffected, since the horizontal tracks already used by the primary power/ground mesh are used for power connection.

主权项

1. A metal oxide semiconductor (MOS) device, comprising:
a set of standard cells extending in a first direction and including at least two standard cells, the set of standard cells comprising at least a portion of a first n-type well (n-well) coupled to a first voltage source; a first isolation region adjacent a first side of the set of standard cells in the first direction, the first isolation region including a first n-well tap; and a second isolation region adjacent a second side of the set of standard cells in the first direction, the second isolation region including a second n-well tap, wherein the first n-well is isolated from a second n-well adjacent to the first n-well by at least one of the first and second isolation regions, the second n-well being coupled to a second voltage source.