发明名称 |
NEGATIVE BITLINE BOOST SCHEME FOR SRAM WRITE-ASSIST |
摘要 |
A device includes a transistor switch coupled between a bit line voltage node and a ground node and a boost signal circuit coupled to a gate node of the transistor switch, where the boost signal circuit providing a boost signal responsive to a write enable signal. The device also includes a first delay element and a first capacitor in series with the first delay element. The first capacitor has a first end coupled to the bit line voltage node and a second end coupled to the gate node through the first delay element. |
申请公布号 |
US2015262655(A1) |
申请公布日期 |
2015.09.17 |
申请号 |
US201514727931 |
申请日期 |
2015.06.02 |
申请人 |
TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. |
发明人 |
HSIEH Wei-Jer;LIN Yangsyu;LU Hsiao Wen;CHENG Chiting;CHANG Jonathan Tsung-Yung |
分类号 |
G11C11/419 |
主分类号 |
G11C11/419 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
Hsin-Chu TW |