发明名称 SEMICONDUCTOR DEVICE
摘要 To provide a semiconductor device which includes a novel refresh circuit in a memory including an oxide semiconductor film. As circuits which operate in a refresh operation of the memory including the oxide semiconductor film, a sense amplifier circuit, a latch circuit, a first switch, and a second switch are provided. In the refresh operation, a potential which reflects a potential stored in the memory is input to the sense amplifier circuit, an output of the sense amplifier circuit is input to the latch circuit, and an output of the latch circuit is written to the memory again through the first switch and a first transistor including an oxide semiconductor in a channel.
申请公布号 US2015262642(A1) 申请公布日期 2015.09.17
申请号 US201514645049 申请日期 2015.03.11
申请人 SEMICONDUCTOR ENERGY LABORATORY CO., LTD. 发明人 KOYAMA Jun
分类号 G11C11/406;G11C11/4093;G11C11/4091;G11C5/10;G11C11/24 主分类号 G11C11/406
代理机构 代理人
主权项 1. A semiconductor device comprising: a memory cell; a sense amplifier circuit; a latch circuit; a first switch; a second switch; and a driver circuit, wherein the sense amplifier circuit, the latch circuit, the first switch, and the second switch operate in a refresh operation of the memory cell, wherein the memory cell includes a first transistor, a second transistor, and a capacitor, wherein the first transistor includes an oxide semiconductor in a channel formation region, wherein one of a source and a drain of the first transistor is electrically connected to a first wiring, wherein the other of the source and the drain of the first transistor is electrically connected to one terminal of the capacitor, wherein the other of the source and the drain of the first transistor is electrically connected to a gate of the second transistor, wherein one of a source and a drain of the second transistor is electrically connected to the first wiring, wherein a gate of the first transistor is electrically connected to a second wiring, wherein the other terminal of the capacitor is electrically connected to a third wiring, wherein the other of the source and the drain of the second transistor is electrically connected to a fourth wiring, wherein a first input terminal of the sense amplifier circuit is electrically connected to the first wiring, wherein an output terminal of the sense amplifier circuit is electrically connected to an input terminal of the latch circuit, wherein an output terminal of the latch circuit is electrically connected to one terminal of the first switch, wherein the other terminal of the first switch is electrically connected to the first wiring, wherein one terminal of the second switch is electrically connected to the first wiring, and wherein the other terminal of the second switch is electrically connected to the driver circuit.
地址 Atsugi-shi JP