DELAY LOCKED LOOP

摘要

A delay locked loop includes a variable delay line circuit configured to delay a pulse selection circuit output to generate an output signal, a delay model circuit to delay the output signal to generate a first feedback signal, a first phase comparator circuit to control the variable delay line circuit according to the input signal and the first feedback signal, a pulse generation circuit to generate a pulse signal according to the input signal and the first feedback signal, a pulse retainer circuit to delay the output signal to generate a second feedback signal, a pulse selection circuit to select the pulse signal generated by the pulse generation circuit or the second feedback signal as the pulse selection circuit output during the tracking operation, and a second phase comparator circuit to control the variable delay line circuit according to the pulse selection circuit output and the output signal.

主权项

1. A delay locked loop for locking a delay between an input signal and an output signal, comprising:
a variable delay line circuit configured to delay a pulse selection circuit output to generate the output signal; a delay model circuit configured to delay the output signal to generate a first feedback signal; a first phase comparator circuit configured to control a delay amount of the variable delay line circuit depending on a phase difference between the input signal and the first feedback signal; a pulse generation circuit configured to generate a pulse signal in response to the input signal and the first feedback signal during a tracking operation; a pulse retainer circuit configured to delay the output signal to generate a second feedback signal during the tracking operation; a pulse selection circuit configured to select the pulse signal generated by the pulse generation circuit or the second feedback signal as the pulse selection circuit output during the tracking operation; and a second phase comparator circuit configured to generate a delay control signal to control the delay amount of the variable delay line circuit depending on a phase difference between the pulse selection circuit output and the output signal during the tracking operation.