PACKED TWO SOURCE INTER-ELEMENT SHIFT MERGE PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS

摘要

A processor includes a decoder to receive an instruction that indicates first and second source packed data operands and at least one shift count. An execution unit is operable, in response to the instruction, to store a result packed data operand. Each result data element includes a first least significant bit (LSB) portion of a first data element of a corresponding pair of data elements in a most significant bit (MSB) portion, and a second MSB portion of a second data element of the corresponding pair in a LSB portion. One of the first LSB portion of the first data element and the second MSB portion of the second data element has a corresponding shift count number of bits. The other has a number of bits equal to a size of a data element of the first source packed data minus the corresponding shift count.

主权项

1. A processor comprising:
a decode unit to receive an instruction, the instruction to indicate a first source packed data operand and a second source packed data operand, each data element in the first source packed data operand to correspond to a different data element in the second source packed data operand to provide a plurality of pairs of corresponding data elements, the instruction also to indicate a third source operand that is to include at least one shift count; and an execution unit coupled with the decode unit, the execution unit operable, in response to the instruction, to store a result packed data operand in a destination storage location, the result packed data operand to include a plurality of result data elements that each correspond to a different pair of corresponding data elements, each result data element to include: a first least significant bit (LSB) portion of a first data element of the corresponding pair of data elements in a most significant bit (MSB) portion of the result data element; and a second MSB portion of a second data element of the corresponding pair of data elements in a LSB portion of the result data element, wherein one of the first LSB portion of the first data element and the second MSB portion of the second data element has a number of bits equal to a corresponding shift count, and wherein another of the first LSB portion of the first data element and the second MSB portion of the second data element has a number of bits equal to a size of a corresponding data element of the first source packed data operand minus the corresponding shift count.