发明名称 CMOS論理ICパッケージの検査方法および検査装置
摘要 <p><P>PROBLEM TO BE SOLVED: To provide a CMOS logical IC package having an electrode for inspection and an inspection method thereof. <P>SOLUTION: There is provided a CMOS logical IC package including the electrode for inspection provided to a position adjacent to each connection electrode pad in the package and a buffer gate. In the CMOS logical IC package inspection method, an opened failure (including disconnection failure and partial disconnection) between the connection electrode pad in the package and an electrode land of the printed wiring board is inspected by measuring a power current produced when an inspection signal of low voltage is applied to the electrode for inspection of the CMOS logical IC package mounted on a printed wiring board. <P>COPYRIGHT: (C)2012,JPO&INPIT</p>
申请公布号 JP5780498(B2) 申请公布日期 2015.09.16
申请号 JP20110117479 申请日期 2011.05.25
申请人 发明人
分类号 G01R31/26;G01R31/02;G01R31/28 主分类号 G01R31/26
代理机构 代理人
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