发明名称 |
A PIPELINED MICROPROCESSOR AND A METHOD RELATING THERETO |
摘要 |
<p>A pipelined microprocessor for processing instructions includes at least one pipeline. The pipeline includes and instruction fetching functional stage, an instruction decoding functional stage, an execution functional stage comprising a number of execution units and a commit functional stage. The commit functional stage includes or is associated with a reorder buffer. Detecting means are provided for detecting instruction irregularities. When an instruction irregularity is detected, an irregularity indication and a flush instruction are generated. The irregularity indication is used to initiate a flush made whereas the flush instruction, when received in a stage or unit set in flush mode, resets the flush mode in said stage/unit.</p> |
申请公布号 |
EP1323033(B1) |
申请公布日期 |
2015.09.16 |
申请号 |
EP20010970460 |
申请日期 |
2001.09.26 |
申请人 |
OPTIS WIRELESS TECHNOLOGY, LLC |
发明人 |
STRÖMBERGSON, JOACHIM;CARLSSON, MAGNUS;VASELL, JONAS |
分类号 |
G06F9/30;G06F9/38 |
主分类号 |
G06F9/30 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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