发明名称 INTELLIGENT DUAL DATA RATE (DDR) MEMORY CONTROLLER
摘要 <p>Various embodiments include systems, methods, and devices configured to reduce the amount of information communicated via system buses/fabrics when transferring data to and from one or more memories. A system master component may send a source address and a destination address to a direct memory access controller inside of, or adjacent to, a memory controller. The direct memory access controller and/or the memory controller may determine whether the source and destination addresses are inside relevant portions of the memory. When both the source and destination are inside the relevant portion of the memory, the memory controller may perform a memory-to-memory data transfer without accessing the system bus.</p>
申请公布号 EP2917842(A1) 申请公布日期 2015.09.16
申请号 EP20130777457 申请日期 2013.10.08
申请人 QUALCOMM INCORPORATED 发明人 GOVINDARAMAN, RAVIKUMAR
分类号 G06F13/16;G06F13/28 主分类号 G06F13/16
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