| 摘要 |
A first vector register 100 stores a first vector of data elements having a vector length, and at least one control register 110 stores control data 115 identifying, independently of the vector length, one or more data elements occupying sequential data element positions within the first vector of data elements. Processing circuitry is responsive to execution of a splice instruction to extract from the first vector each data element identified by the control data, and to output the extracted data elements 125 within a result vector 120 of data elements that also contains data elements 130 from a second vector 105. The control register may be a predicate register. The control data identifies a splice segment to be extracted without reference to the vector length, providing a vector length agnostic approach. Concatenation or merging of vectors is possible, as is rotation (Figure 4). |
