发明名称 合成中に非同期および同期リセット解除を実行するための方法および装置
摘要 <p>A method for designing a system on a target device is disclosed. A system is synthesized by converting a high level description of the system into gates, registers, and reset circuitry. An analysis is performed to identify and remove redundant reset circuitry. The system is optimized after the redundant reset circuitry has been removed. Other embodiments are disclosed.</p>
申请公布号 JP5779237(B2) 申请公布日期 2015.09.16
申请号 JP20130510216 申请日期 2011.05.09
申请人 发明人
分类号 G06F17/50 主分类号 G06F17/50
代理机构 代理人
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