Semiconductor device having junctionless vertical gate transistor and method of manufacturing the same

摘要

A junctionless vertical gate transistor includes an active pillar vertically protruding from a substrate and including a first impurity region, a second impurity region and a third impurity region sequentially formed over the first impurity region; gate electrodes coupled to sidewalls of the second impurity region; and bit lines arranged in a direction of intersecting with the gate electrodes and each contacting the first impurity region. The first to the third impurity regions include impurities of the same polarity.

主权项

1. A semiconductor device comprising:
a plurality of active pillars, each of the active pillars including a first impurity region disposed over a surface of a substrate, a plurality of second impurity regions disposed over the first impurity region, and a plurality of third impurity regions disposed over the plurality of second impurity regions, respectively, wherein the plurality of second impurity regions is arranged at a constant interval over the first impurity region; a gate electrode extending across each of the plurality of active pillars along a row of second impurity regions and disposed over sidewalls of the second impurity regions in the row, wherein the sidewalls of the second impurity regions in the row are each disposed between second impurity regions that are adjacent in a corresponding active pillar of the active pillars; and a bit line disposed between adjacent first impurity regions, disposed under the gate electrode, crossing the gate electrode, and being in contact with one of the adjacent first impurity regions, wherein the first, second, and third impurity regions comprise impurities of the same polarity.