Processor core and multi-core processor system

摘要

In one embodiment of the present invention, processor 1000 comprising a plurality of processor cores for processing an instruction-execution sequence is provided. Signal path 140 that is able to communicate an inter-core interrupt signal fint is connected to at least two processor cores 100A and 100B. Each core of the at least two cores has an inter-core interrupt count setting register (ICSR) 110 and a FIFO counter 120. Inter-core interrupt synchronization function, inter-core interrupt generation function, and FIFO counter updating function are implemented to the every core. In embodiments of the present invention, a core and a method therefor are also provided.

主权项

1. A processor comprising:
a plurality of processor cores for processing a sequence of instruction-execution processes, the sequence including inter-process communications (IPCs), and a signal path that is connected to at least two processor cores of the plurality of processor cores and is able to communicate an inter-core interrupt signal fint, wherein every processor core of the at least two processor cores has
an inter-core interrupt count setting register (ICSR) for storing a FIFO depth value, wherein the FIFO depth value indicates a number of entries in a first-in first-out (FIFO) buffer that is used for IPCs between a process in a present processor core and a process in a different processor core and sets an upper limit for a range in the instruction-execution sequence, the range including the IPCs under execution, anda FIFO counter for storing a value for indicating a number of entries currently used in the FIFO buffer, and wherein, to every processor core of the at least two processor cores implemented in a operable manner are
inter-core interrupt synchronization function that carries out IPCs between a present processor core and a different processor core, based on at least any of: an inter-core interrupt signal fint received from the different processor core of the at least two processor cores, a value in the FIFO counter, and a value in the ICSR,inter-core interrupt generation function that issues and sends an inter-core interrupt signal fint when the present processor core completes accessing the FIFO buffer, the inter-core interrupt signal fint being to be used by the different processor core for controlling its processes, andFIFO counter updating function that increments or decrements a value in the FIFO counter in accordance with a reception of the inter-core interrupt signal fint or with an issuance of an inter-core interrupt signal fint by the present processor core, whereby the processor synchronizes processes on the at least two processor cores for executing the instruction-execution sequence including the IPCs via the FIFO buffer.