High density MOSFET array with self-aligned contacts delimited by nitride-capped trench gate stacks and method

摘要

A high density trench-gated MOSFET array and method are disclosed. It comprises semiconductor substrate partitioned into MOSFET array area and gate pickup area; epitaxial region, body region and source region; numerous precisely spaced active nitride-capped trench gate stacks (ANCTGS) embedded till the epitaxial region. Each ANCTGS comprises a stack of polysilicon trench gate with gate oxide shell and silicon nitride cap covering top of polysilicon trench gate and laterally registered to gate oxide shell. The ANCTGS forms, together with the source, body, epitaxial region, a MOSFET device in the MOSFET array area. Over MOSFET array area and gate pickup area, a patterned dielectric region atop the MOSFET array and a patterned metal layer atop the patterned dielectric region. Thus, the patterned metal layer forms, with the MOSFET array and the gate pickup area, self-aligned source and body contacts through the inter-ANCTGS separations.

主权项

1. A method for fabricating a high density trench-gated MOSFET array device comprising:
a) providing a semiconductor substrate, forming an epitaxial layer on the semiconductor substrate; b) creating an array of active trenches in a MOSFET array area and a pickup trench in a gate pickup area with the active trenches and the pickup trench extending a predetermined total trench depth (TCD) from a top surface of the epitaxial layer into the epitaxial layer; c) creating an array of active nitride-capped trench gate stacks (ANCTGS) upon the active trenches, a pickup nitride-capped trench gate stack (PNCTGS) upon the pickup trench, and implanting into the epitaxial layer body regions and source regions, wherein:
the ANCTGS having predetermined inter-ANCTGS separations; andeach ANCTGS comprises a stack of:
a polysilicon trench gate embedded in a gate oxide shell; anda silicon nitride cap covering the top of the polysilicon trench gate and registered, along a horizontal direction, to the gate oxide shell; and wherein the PNCTGS comprises a stack of:
a polysilicon trench gate embedded in a gate oxide shell; anda pair of silicon nitride caps comprising a center gap registered, along a horizontal direction, to the gate oxide shell, said pair of silicon nitride caps covers, except for the center gap, the top of the polysilicon trench gate thereby forming a MOSFET array in the MOSFET array area and a gate pickup structure in the gate pickup area; and d) depositing a patterned dielectric region atop the MOSFET array and the gate pickup structure and a patterned metal layer atop the patterned dielectric region wherein the patterned metal layer forms a number of self-aligned source and body contacts through the inter-ANCTGS separations in the MOSFET array area and a self-aligned gate contact through the center gap between said pair silicon nitride caps in the gate pickup structure area; and wherein creating the array of active nitride-capped trench gate stacks (ANCTGS) upon the active trenches, and the pickup nitride-capped trench gate stack (PNCTGS) upon the pickup trench further comprises: Forming a polysilicon gate recess inside each active trench and the pickup trench from a top surface of a hard mask; Depositing then dry etching a silicon nitride layer to form a silicon nitride cap seed that just fills up the gate recess in each active trench and only partially fills up the gate recess in the pickup trench; Stripping of the hard mask then depositing and dry etching a second silicon nitride layer to form a silicon nitride cap on top of each active trench gate and a pair silicon nitride cap on top of the pickup trench gate.