RF switch implementation in CMOS process

摘要

A dual pole dual through switch for switching between at least four states. The switch comprises four transistors such as N-channel Metal Oxide Semiconductor transistors, such that at each state at most one transistor is in “on” state, and the others are in “off” state. Each transistor has its own control circuit, which provides zero or negative voltage to the drain of the transistor, positive voltage to the source of the transistor, and control alternating voltage to the gate of the transistor. The switch can be used on-chip for devices. Such devices may include a base station or a handset of a cordless phone.

主权项

1. A radio frequency (RF) switch that is coupled to a receiver, to a transmitter, to a first antenna and to a second antenna; wherein the RF switch comprises:
a first transistor, a second transistor, a third transistor a fourth transistor, a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a fifth capacitor, a sixth capacitor, a seventh capacitor, and an eight capacitor; wherein only the first capacitor, the first transistor and the second capacitor are connected between the transmitter and the first antenna; wherein only the third capacitor, the second transistor and the fourth capacitor are connected between the receiver and the first antenna; wherein only the fifth capacitor, the third transistor and the sixth capacitor are connected between the transmitter and the second antenna; wherein only the seventh capacitor, the fourth transistor and the eighth capacitor are connected between the receiver and the second antenna; first, second, third and fourth control circuits configured to control the first, second, third and fourth transistors respectively and to place only one of said four transistors in an on state while placing the remaining three transistors in a reverse biased off state; a first low pass filter and termination circuit that is coupled between the first transistor and the first control circuit; a second low pass filter and termination circuit that is coupled between the second transistor and the second control circuit; and a third low pass filter and termination circuit that is coupled between the third transistor and the third control circuit and a fourth low pass filter and termination circuit that is coupled between the fourth transistor and the fourth control circuit; wherein each one of the first, second, third and fourth low pass filter and termination circuits comprises a pair of serially coupled first and second resistors and a pair of capacitors that are coupled in parallel to each other and are coupled to a junction between the first and second resistors.