| 主权项 |
1. A manufacturing method of an electric power semiconductor device comprising:
selectively injecting impurities of a second conductivity type into a surface of a second semiconductor layer of a first conductivity type, the second semiconductor layer being provided on a first semiconductor layer of the first conductivity type and having a lower concentration of impurities of the first conductivity type than the first semiconductor layer, to form a plurality of first implantation layers into which the impurities of the second conductivity type have been selectively injected, the plurality of first implantation layers being spaced from each other along the surface of the second semiconductor layer in a first direction; forming a first trench between a first non-implantation region, which is a portion of the second semiconductor layer between an adjacent pair of first implantation layers in the plurality of first implantation layers, and one of the first implantation layers in the adjacent pair of first implantation layers, the first trench extending from the surface of the second semiconductor layer into the second semiconductor layer; forming an epitaxial layer of the first conductivity type to cover the plurality of first implantation layers, the first non-implantation region, and the first trench, as a result of which an unfilled cavity is formed in the first trench; selectively injecting impurities of the second conductivity type into a surface of the epitaxial layer to form a plurality of second implantation layers into which the impurities of the second conductivity type have been selectively injected, the plurality of second implantation layers being spaced from each other along the surface of the epitaxial layer in the first direction; forming a second trench between a second non-implantation region, which is a portion of the epitaxial layer between an adjacent pair of second implantation layers in the plurality of second implantation layers, and one of the second implantation layers in the adjacent pair of second implantation layers, the second trench being above the first trench and extending from the surface of the epitaxial layer into the epitaxial layer; forming a third semiconductor layer of the first conductivity type by epitaxial growth to cover the plurality of second implantation layers, the second non-implantation region, and the second trench, as a result of which an unfilled cavity is formed in the second trench; applying a heat treatment to form first diffusion layers from the plurality of first implantation layers, and second diffusion layers from the plurality of second implantation layers, at least one of the first diffusion layers and at least one of the second diffusion layers being coupled to each other; forming a fourth semiconductor layer of the second conductivity type in the third semiconductor layer, the fourth semiconductor layer being electrically connected to the at least one of the second diffusion layers; forming a fifth semiconductor layer of the first conductivity type in the fourth semiconductor layer, the fifth semiconductor layer having a higher concentration of the impurity of the first conductivity type than the third semiconductor layer; forming a gate electrode, via a gate insulating film, on the third semiconductor layer, on the fourth semiconductor layer, and on the fifth semiconductor layer; forming a first electrode, which is electrically connected to the first semiconductor layer; and forming a second electrode, which is electrically connected to the fourth semiconductor layer and the fifth semiconductor layer. |
