Digital filter for reducing the sampling rate of an input signal

摘要

A digital filter for reducing a sampling rate for an input signal includes a parallelizing block for splitting the input signal into at least two parallel raw signals, an integration block for converting the parallel raw signals into an intermediate signal, and a differentiation block for generating an output signal by differentiating the intermediate signal. The integration block includes a logic block that is designed for generating two parallel sum signals from the parallel raw signals using summation operations, and a recursion block that is designed for generating the intermediate signal recursively from the parallel sum signals.

主权项

1. A digital filter, the digital filter comprising:
a parallelizing hardware block configured to split an input signal into at least two parallel raw signals ue; an integration hardware block configured to convert the parallel raw signals ue into an intermediate signal SR; a differentiation hardware block configured to generate an output signal by differentiating the intermediate signal SR; wherein the integration hardware block includes a logic block configured to generate two parallel sum signals S0 and S1 in accordance withS0⁡(i)=∑e=0E-1⁢⁢ue⁡(i),⁢i=1,2,…andS1⁡(i)=E·u0⁡(i)+…+2·uE-2⁡(i)+uE-1⁡(i),⁢i=1,2,…from the parallel raw signals ue using summation operations, wherein ue(i) is the parallel raw signals and E is the number of parallel raw signals, and
wherein the integration hardware block includes a recursion block configured to generate the intermediate signal SR recursively from the parallel sum signals S0 and S1, wherein the digital filter is configured to reduce a sampling rate of the input signal.