Data processing system with latency tolerance execution

摘要

A data processing system comprises a processor unit that includes an instruction decode/issue unit including a re-order buffer having entries that include an execution queue tag that indicates an execution queue location of an instruction to which a re-order buffer entry is assigned, a result valid indicator to indicate that a corresponding instruction has executed with a status bit valid result, and a forward indicator to indicate that the status bit can be forwarded to an execution queue of an instruction pointed to that is waiting to receive the status bit.

主权项

1. A data processing system comprising:
an instruction decode/issue unit including a re-order buffer having entries; a plurality of execution queues configured to store instructions received from the instruction decode/issue unit and waiting to be executed; and a plurality of execution units coupled to the plurality of execution queues, wherein each execution unit is configured to receive instructions from the plurality of execution queues, wherein each entry in the re-order buffer is configured to store:
an execution queue tag that indicates an execution queue location of an instruction to which a re-order buffer entry is assigned;a result valid indicator to indicate that a corresponding instruction has executed with a status bit valid result;a forward indicator to indicate that a status bit can be forwarded to an execution queue of an instruction that is waiting to receive the status bit;the status bit;a link indicator to indicate a second instruction will use the status bit, wherein the re-order buffer is configured to:
receive a re-order buffer tag from an executed instruction;set the result valid indicator of the re-order buffer entry corresponding to the re-order buffer tag;if the forward indicator is set in the re-order buffer entry corresponding to the re-order buffer tag,
send the execution queue tag to the plurality of execution queues to clear a status pending indicator in the corresponding execution queue location for a pending instruction, andforward the status bit from the executed instruction to the pending instruction with the corresponding execution queue tag,when the link indicator is set,
send the execution queue tag to the plurality of execution queues from a next entry in the re-order buffer to clear the status pending indicator in a corresponding execution queue location for the second pending instruction,forward the status bit from the executed instruction to a second pending instruction with a corresponding second execution queue tag,write the status bit into the next entry in the re-order buffer, andset the result valid indicator of the next entry in the re-order buffer.