Front-end circuit with electro-static discharge protection

摘要

A termination circuit configured to provide electrostatic discharge (ESD) protection is provided. Termination sub-circuits are coupled in parallel, each including respective pull-up and pull-down circuits. Each pull-up circuit has two transistors of a first type coupled in series between a data input and Vdd, a gate of one of the two transistors being coupled to a control input and a gate of the other one of the two transistors being coupled to a first enable input of the termination sub-circuit. Each pull-down circuit has two transistors of a second type coupled in series between the data input and Vss or ground, a gate of one of the two transistors being coupled to the control input and the gate of the other one of the two transistors being coupled to a second enable input of the termination sub-circuit.

主权项

1. A circuit configured to provide electrostatic discharge (ESD) protection, comprising:
a data input and a control input; a plurality of termination sub-circuits coupled in parallel, each termination sub-circuit including:
a pull-up circuit having two transistors of a first type coupled in series between the data input and a first supply voltage (V1), one of the two transistors of the first type having a gate coupled to the control input and the other one of the two transistors of the first type having a gate coupled to a first enable input of the termination sub-circuit, the two transistors of the first type having body diodes biased to implement a first voltage clamp that limits voltage level of the data input to a level of V1+2*Vd, wherein Vd is the voltage drop of each body diode; anda pull-down circuit having two transistors of a second type coupled in series between the data input and a second supply voltage (V2), one of the two transistors of the second type having a gate coupled to the control input and the other one of the two transistors of the second type having a gate coupled to a second enable input of the termination sub-circuit, the two transistors of the second type having body diodes biased to implement a second voltage clamp that limits the input voltage to a level of V2−2*Vd.