发明名称 Command-triggered on-die termination
摘要 An integrated circuit device transmits to a dynamic random access memory (DRAM) one or more commands that specify programming of a digital control value within the DRAM, the digital control value indicating a termination impedance that the DRAM is to couple to a data interface of the DRAM in response to receiving a write command and during reception of write data corresponding to the write command, and that the DRAM is to decouple from the data interface after reception of the write data corresponding to the write command. Thereafter, the integrated circuit device transmits to the DRAM a write command indicating that write data is to be sampled by a data interface of the DRAM during a first time interval and that cause the DRAM to couple the termination impedance to the data interface during the first time interval and decouple the termination impedance from the data interface after the first time interval.
申请公布号 US9135206(B2) 申请公布日期 2015.09.15
申请号 US201414560357 申请日期 2014.12.04
申请人 Rambus Inc. 发明人 Oh Kyung Suk;Shaeffer Ian P.
分类号 H03K17/16;G06F13/40;G11C11/4093;H03K19/0175;G11C11/401;H03K19/00 主分类号 H03K17/16
代理机构 代理人 Shemwell Charles
主权项 1. A method of controlling a dynamic random access memory device (DRAM), the method comprising: transmitting to the DRAM one or more commands that specify programming of a digital control value within the DRAM, the digital control value indicating a termination impedance that the DRAM is to couple to a data interface of the DRAM in response to receiving a write command and during reception of write data corresponding to the write command, and that the DRAM is to decouple from the data interface after reception of the write data corresponding to the write command; and transmitting to the DRAM a write command indicating that write data is to be sampled by the data interface of the DRAM during a first time interval and, as a consequence of transmitting the one or more commands that specify programming of the digital control value, to cause the DRAM to couple the termination impedance to the data interface during the first time interval and decouple the termination impedance from the data interface after the first time interval.
地址 Sunnyvale CA US