Data processing apparatus including reconfiguarable logic circuit

摘要

There is provided a data processing apparatus (1) including a logic circuit (10) that is reconfigurable in each cycle and a library (2) that stores hardware control information (20). The hardware control information (20) includes a plurality of pieces of cycle-based mapping information (21) for individually mapping a plurality of cycle-based circuits, which each realize a function in each cycle for executing an application, onto the logic circuit (10) and configuration selection information (22) for selecting at least one of the plurality of pieces of cycle-based mapping information according to an execution state of the application. The data processing apparatus (1) includes a control unit (11) that reconfigures at least part of the logic region (10) using at least one of the plurality of pieces of cycle-based mapping information (21) according to a request in each cycle based on the configuration selection information (22).

主权项

1. A generation system for generating hardware control information for controlling a reconfigurable logic circuit, the generation system comprising:
one or more computer processors; a storage device for storing data from the one or more computer processors and outputting the data to the one or more computer processors; and a non-transitory computer-readable memory coupled to the one or more computer processors and storing thereon a plurality of functional units executed on the one or more computer processors, the plurality of functions units including:
a functional unit for generating circuit information of a plurality of cycle-based circuits that each realize a function in each cycle for executing an application and storing the circuit information of the plurality of cycle-based circuits to the storage device;a functional unit for (i) generating composite cycle-based mapping information by extracting, out of a plurality of pieces of cycle-based mapping information for mapping the plurality of cycle-based circuits stored in the storage device onto the logic circuit individually, pieces of cycle-based mapping information that are capable of being merged without obstructing functions in each cycle, (ii) merging the extracted pieces of cycle-based mapping information, and (iii) storing the composite cycle-based mapping information to the storage device; anda functional unit for generating the hardware control information, the hardware control information including the composite mapping information stored in the storage device and configuration selection information for selecting at least one of the plurality of pieces of cycle-based mapping information of the composite cycle-based mapping information according to an execution state of the application.