Method and system for asynchronous successive approximation register (SAR) analog-to-digital converters (ADCs)

摘要

An asynchronous successive approximation register analog-to-digital converter (SAR ADC), which utilizes one or more overlapping redundant bits in each digital-to-analog converter (DAC) code word, is operable to generate an indication signal that indicates completion of each comparison step and indicates that an output decision for each comparison step is valid. A timer may be initiated based on the generated indication signal. A timeout signal may be generated that preempts the indication signal and forces a preemptive decision, where the preemptive decision sets one or more remaining bits up to, but not including, the one or more overlapping redundant bits in a corresponding digital-to-analog converter code word for a current comparison step to a particular value. For example, the one or more remaining bits may be set to a value that is derived from a value of a bit that was determined in an immediately preceding decision.

主权项

1. A system comprising:
a digital-to-analog converter (DAC) operable to generate a reference value according to a previous codeword, the previous codeword having been generated according to an asynchronous successive approximation step; a comparator operable to generate an indication signal according to a comparison between an analog signal level and the reference value; a timer operable to generate a timeout signal that preempts the indication signal; and a logic unit operable to generate a preemptive decision according to the timeout signal, the preemptive decision being a current codeword.