DATA PROCESSING APPARATUS AND METHOD FOR PROCESSING VECTOR OPERANDS

摘要

A data processing apparatus has processing circuitry for processing vector operands from a vector register store in response to vector micro-operations, some of which have control information identifying which data elements of the vector operands are selected for processing. Control circuitry detects vector micro-operations for which the control information specifies that a portion of the vector operand to be processed has no selected elements. If this is the case, then the control circuitry controls the processing circuitry to process a lower latency replacement micro-operation instead of the original micro-operation. This provides better performance than if a branch instruction is used to bypass the micro-operation if there are no selected elements.

主权项

1. A data processing apparatus comprising:
a vector register store configured to store vector operands comprising a plurality of data elements; processing circuitry configured to perform vector processing using vector operands obtained from the vector register store; and control circuitry configured to control said processing circuitry to perform the vector processing in response to vector micro-operations; wherein in response to a vector micro-operation specifying a source vector register and a destination vector register of said vector register store and associated with control information indicating which data elements of a portion of the source vector register are selected elements to be processed by the processing circuitry, the control circuitry is configured to:(a) detect whether the control information satisfies a predetermined condition indicating that said portion of the source vector register does not include any selected elements;(b) if the control information does not satisfy said predetermined condition, control the processing circuitry to process said vector micro-operation to perform a predetermined processing operation using one or more selected elements of said portion of said source vector register, to generate a result to be stored to a portion of the destination vector register corresponding to said portion of the source vector register; and(c) if the control information satisfies said predetermined condition, replace said vector micro-operation with a replacement micro-operation having a lower processing latency than said vector micro-operation and providing the same result for said portion of the destination register as said vector micro-operation in the case where the control information satisfies said predetermined condition, and control the processing circuitry to process said replacement micro-operation.