| 发明名称 |
MEMORY DEVICE |
| 摘要 |
According to one embodiment, an encoder generates a write data parity from write data to memory elements. A decoder corrects an error of read data from the memory elements using a read data parity for the read data and a check matrix. An inverter maintains or inverts all bits of a received input. Calculation by the decoder using the read data, the read data parity, and the check matrix produces a first result when an error is not included in the read data, a second result when an error is included in the read data, a third result when an error is not included in the read data and all bits of the read data are inverted, and a fourth result when an error is included in the read data and all bits of the read data are not inverted. |
| 申请公布号 |
US2015254136(A1) |
申请公布日期 |
2015.09.10 |
| 申请号 |
US201414458783 |
申请日期 |
2014.08.13 |
| 申请人 |
KABUSHIKI KAISHA TOSHIBA |
发明人 |
HOYA Katsuhiko;EGUCHI Yasuyuki |
| 分类号 |
G06F11/10 |
主分类号 |
G06F11/10 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A memory device comprising:
memory elements; an encoder which generates a write data parity from write data to the memory elements; a decoder which corrects an error of read data from the memory elements using a read data parity for the read data and a check matrix; and an inverter which maintains or inverts all bits of a received input, wherein calculation by the decoder using the read data, the read data parity, and the check matrix produces:
a first result when an error is not included in the read data,a second result when an error is included in the read data,a third result when an error is not included in the read data and all bits of the read data are inverted, anda fourth result when an error is included in the read data and all bits of the read data are not inverted. |
| 地址 |
Tokyo JP |
