ERROR CORRECTION DECODER

摘要

According to an embodiment, an error correction decoder includes a first calculation circuit and a second calculation circuit. The first calculation circuit and the second calculation circuit perform the column processing based on the second reliability information corresponding to variable nodes belonging to each of one or more valid blocks arranged in a first row group and the row processing based on the first reliability information corresponding to variable nodes belonging to one or more valid blocks arranged in a second row group whose processing order is later than that of the first row group in parallel.

主权项

1. An error correction decoder, comprising:
a first storage unit configured to store first reliability information of each of a plurality of bits corresponding to an ECC (Error Correction Code) frame defined by a parity check matrix in which M×N (M and N are integers equal to 2 or greater) blocks are arranged, each of the blocks corresponding to either an invalid block as a zero matrix of p rows×p columns (p is an integer equal to 2 or greater) or a valid block as a nonzero matrix of p rows×p columns; a second storage unit configured to store second reliability information of each of the plurality of bits; a first calculation circuit configured to read the first reliability information corresponding to variable nodes belonging to each of one or more valid blocks arranged in a given row group of the parity check matrix from the first storage unit, to calculate the second reliability information corresponding to the variable nodes by performing row processing based on the first reliability information, and to write the second reliability information to the second storage unit; and a second calculation circuit configured to read the second reliability information corresponding to variable nodes belonging to each of the one or more valid blocks arranged in the given row group of the parity check matrix from the second storage unit, to calculate the first reliability information corresponding to the variable nodes by performing column processing based on the second reliability information, and to write the first reliability information to the first storage unit, wherein the first calculation circuit and the second calculation circuit perform the column processing based on the second reliability information corresponding to variable nodes belonging to each of one or more valid blocks arranged in a first row group and the row processing based on the first reliability information corresponding to variable nodes belonging to one or more valid blocks arranged in a second row group whose processing order is later than that of the first row group in parallel.