发明名称 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
摘要 A digital-correction-type A/D converter which is a charge sharing type and performing successive approximation is realized in a small area. The A/D converter is configured with an A/D conversion unit which is a charge sharing type and performing successive approximation, a digital correction unit which receives a digital output of the A/D conversion unit and performs digital correction to the digital output, and a holding unit which holds a test signal. A test signal of a common value from the holding unit is inputted into the A/D conversion unit in the first period and the second period. The A/D conversion correction coefficient for the digital correction unit is calculated on the basis of the digital correction result of the digital correction unit in the first period, and the digital correction result of the digital correction unit in the second period.
申请公布号 US2015256193(A1) 申请公布日期 2015.09.10
申请号 US201514711733 申请日期 2015.05.13
申请人 RENESAS ELECTRONICS CORPORATION 发明人 OSHIMA Takashi;MATSUURA Tatsuji;OKUDA Yuichi;NAKANE Hideo;YAMAMOTO Takaya;KIMURA Keisuke
分类号 H03M1/12;H03M1/44;H03M1/06;H03M1/00 主分类号 H03M1/12
代理机构 代理人
主权项 1. A communication system comprising: an analog circuit unit receiving a high frequency signal from an antenna; first and second A/D conversion units each receiving first and analog signals outputted from the analog circuit unit; and a test signal generation unit; wherein each of the first and second A/D conversion units comprise: a digital correction unit operable to output an A/D conversion result by performing digital correcting; and a holding unit operable to hold a test signal, wherein the first and second A/D conversion units are of a charge sharing type and operable to perform successive approximation, wherein, at the time of a test, a test signal outputted from the test signal generation unit with the same analog value is inputted to the holding unit in a first period and a second period different from the first period, a first dither signal outputted from the test signal generation unit is inputted to the holding unit in the first period, and an A/D conversion correction coefficient is determined, on the basis of a first digital correction result in the digital correction unit to a first digital output in the first period and a second digital correction result in the digital correction unit to a second digital output from in the second period, and wherein, at the time of a normal operation, the digital correcting is performed with the use of the A/D conversion correction coefficient determined at the time of the test.
地址 Kanagawa JP