DISPLAY DEVICE

摘要

An objective of the present invention is to provide a display device capable of suppressing consumption of the current flowing through gate clock signal bus lines by reducing the loads on the gate clock signal bus lines.;In a shift register, which writes the voltages of a plurality of gate clock signals (CK1 to CK3) to gate bus lines (GL) via buffer circuits (BF), a plurality of gate clock signal bus lines (51a to 54a) are formed in an area between a display portion (600) and the buffer circuits (BF), independently of a clear signal bus line and other lines, so as to be adjacent to the buffer circuits (BF). This results in no area in which clear signal branch lines (61b) cross the gate clock signal bus lines (51a to 54a) and wiring lines in bistable circuits SR. Thus, it is possible to eliminate interlayer capacitance due to the crossings of the lines and fringe capacitance between the lines.

主权项

1. A display device, comprising:
a substrate; pixel circuits formed in a display area on the substrate in which to display an image; a plurality of scanning signal lines formed in the display area, each constituting a part of the pixel circuit; a shift register formed on the substrate and having a plurality of bistable circuits and a plurality of buffer circuits, the bistable circuits having first and second states and being provided in one-to-one correspondence with the scanning signal lines, the buffer circuits being connected in series to the respective bistable circuits so as to, when the bistable circuits are sequentially brought into the first state, output clock signals provided by a plurality of clock signal bus lines for transmitting the respective clock signals, to the scanning signal lines being driven sequentially by the bistable circuits being sequentially brought into the first state; and control signal bus lines formed in an area opposite to the display area with respect to a shift register area in which the shift register is formed, the control signal bus lines transmitting control signals for controlling the operation of the bistable circuits and being connected to the bistable circuits by control signal branch lines, wherein, the buffer circuits are formed in a line within the shift register area so as to be opposed to the display area, and the clock signal bus lines are formed in an area between the shift register area and the display area so as to be adjacent to the buffer circuits.