| 发明名称 |
TIMING MEASURING CIRCUIT |
| 摘要 |
According to one embodiment, a timing measuring circuit is provided with N (N is an integer of 2 or more) delay circuits and a comparison circuit. The N delay circuits delay a reference signal by different delay times. The comparison circuit outputs N timing adjustment values based on results of comparison between the reference signal and N output signals from the delay circuits. |
| 申请公布号 |
US2015256164(A1) |
申请公布日期 |
2015.09.10 |
| 申请号 |
US201414475625 |
申请日期 |
2014.09.03 |
| 申请人 |
KABUSHIKI KAISHA TOSHIBA |
发明人 |
EBATO Yasushi;FUKUDA Nariyuki;HOSAKA Kazuhito;OOIGAWA Isao;YAMAGUCHI Takeshi;ISHIDA Mamoru;BAN Eiji;HAYASHIDA Kazumi |
| 分类号 |
H03K5/13 |
主分类号 |
H03K5/13 |
| 代理机构 |
|
代理人 |
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| 主权项 |
1. A timing measuring circuit, comprising:
N (N is an integer of 2 or more) delay circuits that delay a reference signal by different delay times; and a comparison circuit that outputs N timing adjustment values based on results of comparison between the reference signal and N output signals from the delay circuits. |
| 地址 |
Minato-ku JP |
