METHOD AND APPARATUS FOR CALIBRATING WRITE TIMING IN A MEMORY SYSTEM

摘要

A system that calibrates timing relationships between signals involved in performing write operations is described. This system includes a memory controller which is coupled to a set of memory chips, wherein each memory chip includes a phase detector configured to calibrate a phase relationship between a data-strobe signal and a clock signal received at the memory chip from the memory controller during a write operation. Furthermore, the memory controller is configured to perform one or more write-read-validate operations to calibrate a clock-cycle relationship between the data-strobe signal and the clock signal, wherein the write-read-validate operations involve varying a delay on the data-strobe signal relative to the clock signal by a multiple of a clock period.

主权项

1. A memory controller comprising:
calibration logic to, in a calibration mode of operation, phase align a strobe signal with a clock signal based on feedback from an integrated circuit (IC) memory device, the feedback indicating whether the strobe signal is edge-aligned with the clock signal, to establish a write-leveled timing relationship; and wherein the calibration logic is to selectively adjust the write leveled timing relationship, by an integer number of cycles of the strobe signal, responsive to whether a first data pattern, written to a location in the IC memory device, matches a second data pattern retrieved from the location in the IC memory device.