发明名称 |
SEMICONDUCTOR MEMORY DEVICE AND REFRESH CONTROL SYSTEM |
摘要 |
A semiconductor memory device includes an address latch unit suitable for consecutively latching first refresh addresses, which correspond to successively-activated word lines, from consecutively received addresses for word lines to be activated in response to word line hit signals identifying the successively-activated word lines; an address comparison unit suitable for generating a comparison result signal by comparing the previously latched first address with the currently latched first address; a refresh control unit suitable for selecting a first refresh operation corresponding to the currently latched first address, and a second refresh operation corresponding to a second address in response to the comparison result signal, and a refresh command signal; and a refresh operation unit suitable for performing the first and second refresh operations on memory cells therein according to the selection of the refresh control unit. |
申请公布号 |
US2015255140(A1) |
申请公布日期 |
2015.09.10 |
申请号 |
US201414341451 |
申请日期 |
2014.07.25 |
申请人 |
SK hynix Inc. |
发明人 |
SONG Choung-Ki |
分类号 |
G11C11/406;G11C11/408 |
主分类号 |
G11C11/406 |
代理机构 |
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代理人 |
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主权项 |
1. A semiconductor memory device comprising:
an address latch unit suitable for consecutively latching first refresh addresses, which correspond to successively-activated word lines, from consecutively received addresses for word lines to be activated in response to word line hit signals identifying the successively-activated word lines; an address comparison unit suitable for generating a comparison result signal by comparing the previously latched first address with the currently latched first address; a refresh control unit suitable for selecting one of a first refresh operation corresponding to the currently latched first address, and a second refresh operation corresponding to a second address in response to the comparison result signal, and a refresh command signal; and a refresh operation unit suitable for performing the first and second refresh operations on memory cells therein according to the selection of the refresh control unit. |
地址 |
Gyeonggi-do KR |