发明名称 |
SEMICONDUCTOR DEVICE |
摘要 |
[Problem] To provide a semiconductor device suitable for miniaturization. To provide a highly reliable semiconductor device. To provide a semiconductor device with improved operating speed.;[Solving Means] A semiconductor device including a memory cell including first to cth (c is a natural number of 2 or more) sub memory cells, wherein: the jth sub memory cell includes a first transistor, a second transistor, and a capacitor; a first semiconductor layer included in the first transistor and a second semiconductor layer included in the second transistor include an oxide semiconductor; one of terminals of the capacitor is electrically connected to a gate electrode included in the second transistor; the gate electrode included in the second transistor is electrically connected to one of a source electrode and a drain electrode which are included in the first transistor; and when j≧2, the jth sub memory cell is arranged over the j−1th sub memory cell. |
申请公布号 |
US2015255139(A1) |
申请公布日期 |
2015.09.10 |
申请号 |
US201514637542 |
申请日期 |
2015.03.04 |
申请人 |
Semiconductor Energy Laboratory Co., Ltd. |
发明人 |
ATSUMI Tomoaki;NAGATSUKA Shuhei;MORIWAKA Tamae;ENDO Yuta |
分类号 |
G11C11/24;H01L27/115;H01L27/12;H01L29/24;H01L29/786 |
主分类号 |
G11C11/24 |
代理机构 |
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代理人 |
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主权项 |
1. A semiconductor device comprising:
a memory cell including first to cth (c is a natural number of 2 or more) sub memory cells, wherein: the jth (j is a natural number of 1 to c) sub memory cell includes a first transistor, a second transistor, and a capacitor, a first semiconductor layer included in the first transistor and a second semiconductor layer included in the second transistor include an oxide semiconductor, one of terminals of the capacitor is electrically connected to a gate electrode included in the second transistor, the gate electrode included in the second transistor is electrically connected to one of a source electrode and a drain electrode which are included in the first transistor, and when j≧2, the jth sub memory cell is arranged over the j−1th sub memory cell. |
地址 |
Atsugi-shi JP |