METHOD OF FORMING MAGNETIC TUNNELING JUNCTIONS

摘要

A method for fabricating an MRAM bit that includes depositing a spacer layer that protects the tunneling barrier layer during processing is disclosed. The deposited spacer layer prevents byproducts formed in later processing from redepositing on the tunneling barrier layer. Such redeposition may lead to product failure and decreased manufacturing yield. The method further includes non-corrosive processing conditions that prevent damage to the layers of MRAM bits. The non-corrosive processing conditions may include etching without using a halogen-based plasma. Embodiments disclosed herein use an etch-deposition-etch sequence that simplifies processing.

主权项

1. A method for fabricating a magnetic random access memory bit, the method comprising:
introducing into a processing chamber a stack, wherein the stack comprises:
a conductive hardmask layer;a top electrode layer comprising a ferromagnetic layer, wherein the top electrode layer is positioned below the conductive hardmask layer;a tunneling barrier layer, wherein the tunneling barrier layer is comprised of a dielectric material, and wherein the tunneling barrier layer is adjacent to the top electrode layer;a bottom electrode layer comprising a ferromagnetic layer, and wherein the bottom electrode layer is adjacent to the tunneling barrier layer; anda substrate, wherein the substrate is positioned below the bottom electrode layer; etching the top electrode layer and the tunneling barrier layer, thereby exposing the sidewalls of the tunneling barrier layer; depositing a spacer layer over the sidewalls of the tunneling barrier layer and at least some of the bottom electrode layer, thereby forming a sub-stack comprising the portions of the bottom electrode layer and the portions of the spacer layer that are adjacent to each other; and etching the stack, wherein the etching process:
etches at least some of the sub-stack down to the substrate; andleaves the sidewalls of the tunneling barrier layer covered by the spacer layer.